PSI2488-U9 GPON IP Brief

Description

PSI2488-U9 is a GPON ONT SERDES capable of receiving serial data at the rate of 2.488Gbps and transmitting data at the rate of 1.244Gbps. The transmitter serializes 8 bit parallel data to a differential serial output, and the receiver de-serializes the differential serial data input to 16 bit parallel data output. The transmitter has a clock generator to generate clocks to serialize the data. The amplitude level of the TX output driver is programmable. There is a Squelch circuit at the receiver input to detect the loss of signal. Parallel loopback and serial loopback capabilities are implemented to be able to test the entire channel. To have more flexibility the reference clock can be any of 19.44, 38.8, 77.76 or 155.52MHz. A 2.5V power supply is used for the output stage of the TX output driver, and the rest of the IP has a flexibility to operate with either 1V or 1.2V supply. There is no external components such as resistors or capacitors used for the IP. Jitter tolerance and jitter generation of the IP is way beyond the jitter requirements making the IP suitable for very noisy environment. PSI2488-U9 is fabricated in UMC’s 90nm process.

 

Features

• Receiver capable of operating at 2.488Gbps (and 1.244Gbps for testing).
• Transmitter capable of operating at 1.244Gbps (and 2.488Gbps for testing).
• Jitter generation, jitter tolerance and jitter transfer are in compliance with the GPON standard.
• Programmable TX output amplitude level.
• Flexible options for reference clock at 19.44, 38.8, 77.76 or 155.52MHz.
• Capability for the loss of signal detection.
• On-chip parallel loopback capability for testing.
• On-chip serial loopback capability for testing.
• 2.5V supply for the TX output and 1V (or 1.2V) supply for the rest of the IP.
• UMC 90nm CMOS process.

 

Special features distinguishing PSI2488-U9 from other GPONs in the market

• Jitter performances are much better than the spec requirements.
• Capable of operating with 1V or 1.2V supply.
• No external components.

The following Eye Diagram shows the TX output under the following conditions:

The pattern generator generates PRBS 2^31-1 pattern at 2.488Gbps rate. This signal goes through the OLT and ONT OE modules. It then goes to RX input, and the recovered clock goes to the TX as the reference clock to serialize the data. The rate at the TX output is 1.244Gbps.

The eye diagram shows a peak to peak jitter of about 50ps which is about 0.06UI. This is something less than one third of the maximum allowed jitter generation.